SOI technology consists in separating a fine silicon layer (a few nanometers) on a silicon substrate by a relatively thick layer of insulator (a few tens of nanometers as a general rule).
Integrated circuits produced in SOI technology exhibit a certain number of advantages. Such circuits generally exhibit lower electrical consumption for equivalent performance. Such circuits also bring about lower junction capacitances, which make it possible to improve switching speed. Moreover, the phenomenon of spurious triggering (referred to as “latchup”) encountered by “bulk” technology metal-oxide-semi-conductor (MOS) transistors can be avoided. Such circuits therefore turn out to be particularly suitable for applications of SoC (“Systems on Chip”) or MEMS (“Micro Electro-Mechanical Systems”) type. It is also noted that SOI integrated circuits are less sensitive to the effects of ionizing radiations and thus turn out to be more reliable in applications where such radiations can bring about operating problems, notably in space applications. SOI integrated circuits can notably comprise random-access memories of SRAM (“Static Random Access Memory”) type and logic gates.
The reducing of the static consumption of logic gates while increasing their toggling speed forms the subject of much research. Certain integrated circuits under development integrate both low-consumption logic gates and also logic gates with high toggling speed. To generate these two types of logic gates on one and the same integrated circuit, the threshold voltage (abbreviated VT) of certain transistors is lowered to form logic gates with high toggling speed, and the threshold voltage of other transistors is increased to form low-consumption logic gates. In “bulk” technology, the modulation of the threshold voltage level of transistors of the same type is performed by making the doping level of their channel different. However, in fully depleted channel semi-conductor on insulator technology, better known by the acronym FDSOI (for “Fully Depleted Silicon On Insulator”), the doping of the channel is almost zero (1015 cm−3). Thus, the doping level of the channel of the transistors cannot therefore exhibit any significant variations, thereby preventing the threshold voltages from being made different in this fashion. A solution proposed in certain studies, to produce transistors of the same type with distinct threshold voltages, is to integrate various gate materials for these transistors. However, the practical production of such an integrated circuit turns out to be technically tricky and economically prohibitive.
In order to have distinct threshold voltages for various transistors in FDSOI technology, it is also known to use an electrically biased ground plane (or “back plane”) disposed between a thin insulating oxide layer and the silicon substrate. By altering the doping of the ground planes and their electrical bias, it is possible to improve the electrostatic control of these transistors, thereby making it possible to define various ranges of threshold voltages for these transistors. It is thus possible to provide so-called LVT (for “Low VT”) low threshold voltage transistors, so-called HVT (for “High VT”) high threshold voltage transistors, and so-called SVT (for “Standard VT”), or RVT (for “Regular VT”) intermediate threshold voltage transistors. Typically, LVT transistors exhibit a threshold voltage of less than or equal to 350 mV, HVT transistors greater than or equal to 500 mV and RVT transistors between 350 mV and 500 mV.
Such transistors are described, for example, in the technical application note of P. Flatresse et al., “Planar fully depleted silicon technology to design competitive SOC at 28 nm and beyond”, STMicroelectronics, 2012, available on the Internet site “www.soiconsortium.org”.
In a known manner, such transistors exhibiting different threshold voltages can be integrated within one and the same integrated circuit. Such co-integration makes it possible notably to benefit from several threshold voltage spans, together with better operating flexibility of the circuit. However, this co-integration can lead to a degradation in electrical performance of the circuit, or else bring about violations of drafting rules during circuit design steps.
Typically, the transistors are placed in the circuit within so-called standard cells. These standard cells generally each comprise solely transistors of a given threshold voltage level. These cells are typically placed alongside one another, so as to form rows of cells, parallel to one another.
Generally, in the presence of cells having distinct threshold voltages, it is preferable to co-integrate the cells exhibiting different threshold voltages within same rows. Indeed, placing cells with distinct threshold voltage along rows of cells with homogeneous threshold voltage can lead to difficulties with the circuit design (increase in length of electrical interconnections between cells, overconsumption of occupied surface area) which, ultimately, attenuate the advantages afforded by co-integration.
However, placing cells with distinct threshold voltages in one and the same row can lead to other difficulties. Notably, the steep discontinuity between semi-conducting wells of the various cells can lead to the formation of singular points. These singular points are situated at the junction between four wells exhibiting pairwise opposite dopings. These singular points can lead, according to the electrical biases applied to the wells, to the appearance of leakage currents caused by the forward bias of p-n junctions formed by these wells.